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Rtd FPGA35S6100HR Manual de usuario Pagina 19

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RTD Embedded Technologies, Inc. | www.rtd.com 19 FPGA35S6 User’s Manual
Table 11: P2 and P3 Pin Assignments
IDAN P2 Pin
Signal
Pull
Jmpr
CN4
Pin
IDAN P3 Pin
Signal
Pull
Jmpr
C9 Pin
Row 1
Row 2
Row 3
Row 1
Row 2
Row 3
36
GND
44
36
GND
44
57
port0_p[11]
45
57
port1_p[11]
45
16
GND
46
16
GND
46
37
port0_n[11]
47
37
port1_n[11]
47
58
GND
48
58
GND
48
17
+5V
49
17
+5V
49
38
GND
50
38
GND
50
59
Reserved
59
Reserved
18
Reserved
18
jtag_vref
CN3.2
39
Reserved
39
GND
CN3.3
60
Reserved
60
jtag_tms
CN3.4
19
Reserved
19
GND_TCK
CN3.5
40
Reserved
40
jtag_tck
CN3.6
61
Reserved
61
GND
CN3.7
20
Reserved
20
jtag_tdo
CN3.8
41
Reserved
41
GND
CN3.9
62
Reserved
62
jtag_tdi
CN3.10
21
Reserved
21
Reserved
42
Reserved
42
Reserved
P4: High Speed Digital I/O Connector
Connector Part #: VALCONN HDB-62S Mating Connector: VALCONN HDB-62P
Connector P4 provides 40 digital I/O lines, along with a +5V pin and ground pins. These signals are 3.3V tolerant. The signal names reflect the
signal names I n the Xilinx UCF file with the device pin out.
P4 is attached to Bank 1, and supports any of the Spartan 6 I/O Standards that use a 3.3V V
CCO
and no reference voltage. This includes
LVTTL, LVCMOS33 input and output, and LVDS_33 input. LVDS output is not supported in Bank 1.
Table 12: P4 Pin Assignments
IDAN P4 Pin
Signal
C8 Pin
Row 1
Row 2
Row 3
1
Port2_p[0]
1
22
Port2_n[0]
2
43
Port2_p[1]
3
2
Port2_n[1]
4
23
Port2_p[2]
5
44
Port2_n[2]
6
3
Port2_p[3]
7
24
Port2_n[3]
8
45
GND
9
4
GND
10
25
Port2_p[4]
11
46
Port2_n[4]
12
5
Port2_p[5]
13
26
Port2_n[5]
14
47
Port2_p[6]
15
6
Port2_n[6]
16
27
Port2_p[7]
17
48
Port2_n[7]
18
7
GND
19
28
GND
20
49
Port2_p[8]
21
8
Port2_n[8]
22
29
Port2_p[9]
23
50
Port2_n[9]
24
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