Rtd FPGA35S6100HR Manual de usuario descargar pdf (Pagina 23)

RTD Embedded Technologies, Inc. | www.rtd.com 23 FPGA35S6 User’s Manual

5 Functional Description

5.1 Block Diagram

The Figure below shows the functional block diagram of the FPGA35S6. The various parts of the block diagram are discussed in the following

sections.

Figure 7: FPGA35S6 Block Diagram

5.2 Oscillator

The FPGA35S6 features a 27 MHz oscillator for clock based operations in the FPGA.

5.3 EEPROM

The FPGA35S6 features a 256 x 16 SPI EEPROM, ATMEL AT93C66A. For information on the AT93C66A refer to http://www.atmel.com/

5.4 DDR2 SRAM

The FPGA35S6 features a 1Gb DDR2 SRAM, MT47H64M16HR 25E. This is interface to the Spartan 6 FPGA using Xilinx Memory Interface

Generators (MIG) core. The example FPGA code has demonstrated how to use this core in a FPGA design.

PCIe Bus

PCIe x1

Link

Xilinx

Spartan 6

Oscillator

Level Shifter

Digital I/O CN4 and CN9

DDR2 SRAM

High Speed Digital I/O CN8

EEPROM

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Rtd FPGA35S6100HR Manual de usuario Pagina 23